Working at STT

Spin Transfer Technologies (STT) is focused on the development of novel magnetoresistive random access memory (MRAM) technologies and devices in collaboration with New York University researchers and industry partners.

STT is an equal opportunity employer offering competitive benefits.

Positions

Description

You will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry. You will direct cell, block, and array layout activities for library and full chip projects. Activities will include interfacing with multi-discipline design teams, develop schedule timelines for layout execution and leading your team to implement it, skill development to grow the capabilities of your Physical Design team, developing and implementing methodology improvements to ensure better efficiency and effectiveness, making in-house versus outsource recommendations.

Qualifications

Candidate should have 10+ years of directly relevant layout and leadership experience. Bachelor of Science degree a plus.

  • Demonstrated leadership skills with a strong background in layout
  • Extensive experience in Full Chip layout planning & assembly with a background in memory layout, arrays and hierarchy
  • Thorough knowledge of layout of Analog/Mixed signal circuit blocks and the physical layout requirements
  • Extensive experience in performing DRC/LVS/ERC/Antenna EM and IR analysis and other checks, R&C extraction for different layout levels
  • Ability to generate LEF’s for use by customers
  • Must have strong skills in layout, floor planning, and manual routing
  • Strong understanding of device optimization, component matching, minimizing parasitics, including techniques to minimize manufacturing variations
  • Knowledge of semiconductor wafer fabrication steps to support layout development using proper CAD layers
  • Knowledge of Cadence and Mentor Graphics tools
  • A self-starter who is pro-active, a fast learner, detail oriented, and team oriented

Submit your resume for Layout Design Consultant

Description

As a member of our MRAM design team you will develop custom analog circuits for a variety of new MRAM memory devices. You will design, model, and verify critical custom circuits used in our MRAM memory devices. In the design phase you will also oversee the circuit layout and verify post-layout performance as well as integration into the full chip-level assembly. During design validation you will drive the analysis of the blocks you designed. This position requires demonstrated custom analog design experience.

Qualifications

Candidate should possess a Bachelor or Master of Science degree in Electrical Engineering with 5+ years of directly relevant experience in custom IC circuit design:

  • Significant recent experience with analog design, circuit verification and optimization
  • Experience with layout floor-planning
  • Significant experience with verification of parasitic extractions of the circuits
  • Proficiency performing analog, mixed signal, and co-sim simulations using standard industry simulators
  • Experience with Cadence analog design flow with tools such as Hspice, Spectre, HSIM, Ultrasim, XA
  • Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
  • Experience with multi-gigabit CMOS technology
  • Timing generator, bandgap circuit design, current and voltage reference generation, operational amplifier circuits, and sense amplifier circuits experience is a plus
  • Demonstrate a high level of self-motivation

Submit your resume for MRAM Memory Design Engineer

Description
You will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry. You will direct cell, block, and array layout activities for library and full chip projects. Activities will include interfacing with multi-discipline design teams, develop schedule timelines for layout execution and leading your team to implement it, skill development to grow the capabilities of your Physical Design team, developing and implementing methodology improvements to ensure better efficiency and effectiveness, making in-house versus outsource recommendations.

Responsibilities
Work as an R&D Engineer in the MTJ structure development department at Spin Transfer Technologies, Fremont, California. Candidate will be responsible for developing, characterizing and implementing new MTJ processes and structures for novel MRAM applications. Job requires interfacing and collaborating with other departments within the R&D organization.

Organization
Spin Transfer Technologies

Location
Fremont, California

Job
Engineering, Full-time

Requirements:

  • M.S./Ph.D. in Physics, Materials Science Engineering, Chemistry or related field
  • Minimum 5 years of relevant experience in magnetic thin film development and characterization
  • Experience in magnetic materials, multilayers and MTJ devices for MRAM applications
  • Hands-on experience in the operation of R&D and Manufacturing types of equipment
  • Hands-on experience in PVD sputtering systems operation and thin film deposition
  • Magnetic thin film characterization techniques: VSM, MOKE, Torque Magnetometer, FMR
  • Physical film analysis techniques such as: SEM, TEM , XPS, XRD, AFM is a plus
  • Able to work in fast paced environment
  • Innovative, detail-oriented and have strong oral and written communication skills
  • Data analysis using JMP, Excel, basic knowledge of Python, LabVIEW is a plus

Submit your resume for MTJ Structure/Thin Film Materials Development Engineer

Description
As an MRAM device characterization scientist/engineer you will be part of a highly motivated, dynamic and fast moving team developing spin transfer torque magneto-resistive random access memory (STT-MRAM).

The key responsibilities include:

  • Collection and interpretation of electrical and magnetic test data from both individual devices as well as large statistical samples from memory arrays
  • Analysis and evaluation of test data to constantly improve the performance of STT-MRAM devices
  • Reporting and presenting test results to the other teams within the company
  • Development of advanced MRAM characterization techniques to constantly improve test and characterization capabilities
  • Interacting closely with magnetic thin film, device fabrication and chip design teams

Qualifications:

  • M.S. or Ph.D. in physics or electrical engineering with strong back ground in solid state physics and devices, with proven expertise in magnetism, MRAM devices, and/or spintronics preferred
  • Significant experience with electrical test and measurement systems
  • Some experience with Labview programming required
  • Strong presentation and communication skills
  • Familiarity with statistical data analysis methods, experience with SAS JMP preferred

Submit your resume for MRAM Device Characterization Scientist/Engineer